Networking, Specman E, digital logic, Constrained-random verification, IP subsystem SoCs, Debug, Verification, systemverilog

Fpga, Perl, Python, low power verification, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, RTL development environments, transaction level modelling, test bench infrastructure, verification platforms, formal verification methods, emulation platforms

Verilog, System Verilog, Asic verification, Uvm, cpu design, DDR4, Memory

DDR, Ovm, System Verilog, FPGA verification, protocol verification, validation test suites, Uvm, constrained random verification methodologies, FPGA prototyping, FPGA architecture

Ethernet, Python, Pcie, BERTs, DCAs, Network Analyzers, Oscilloscopes, characterization NRZ and PAM-4, high-speed SerDes validation, Communication Protocols

Excel, Python, Ms Word

Tcl Scripting, Doors, DO-254 development process, Electronics Electrical Engineering, Knowledge of Hardware Board and different components like ADC DAC Serial Memory, RTL development using VHDL, Hardware system design knowledge of digital logic, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, FPGA Synthesis Place and Route, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA design tools like Libero