Fpga, Debugging, Soc, engineering services, Dft, Scheduling, Mixed Signal

Tcl, Jtag, Perl, Cadence Tools, BSCAN, Dft, Compression Testing

Scan Insertion, DFT methodology, Fault modeling, EDA Applications

Unix, Linux Os, Verilog, Tcl, Ruby, Jtag, Python, Perl, Scripting Languages, SV, MBIST, IO-PHY loopback testing, systemverilog, DFT feature verification, file version control, EDA simulation tools, Cadence NCSIM, UVM verification methodologies, Verdi, SVA, Synopsys VCS, fuse, Scan, debug tools

Tcl, Jtag, Awk, Sed, LBIST, MBIST, gate-level simulation, Scan, ATPG, Dft, Spyglass-DFT, Tessent

logic bist , C, Verilog, Tcl, Jtag, Python, Perl, SAF, BSCAN, SDF annotated gate level verification, IEEE1149.1, Scan Codec insertion, ATPG, ATPG Fault models, Fault Simulation, PDT, VHDL, IEEE1687, Scan and Memory Diagnosis, TDF, SDD, Memory BIST and Repair implementation