Test Plan Creation, Regression Analysis, SV assertions, Formal verification methods, Uvm, Coverage-driven verification, systemverilog

Verilog, System Verilog, SiFive RISC processor, VCS tool, UVM Concept, Functional Code coverage

Vcs, Pcie, Python, Perl, Ethernet, Tcl, Xcelium, Uvm, Testbench Architecture, LPDDR4, Functional Coverage, Verdi, UCIe, systemverilog, Axi, MIPI, Constrained Random Verification, APB, DVE, USB4, USB3, Questa, CXL, DDR5, DDR4, AHB, SVA

Soc Architecture, System Verilog, digital design concepts, UVM Universal Verification Methodology, debugging using waveforms and logs

code coverage , Regression Analysis, Test Plan Creation, formal verification, SV assertions, Uvm, coverage-driven verification, systemverilog, functional coverage

Shell, Perl, Verilog, System Verilog, Python, Tcl, Uvm