code coverage , closure , automation, Ovm, Tcl Scripting, Verilog, Perl, SDF, GLS, Uvm, RTL, SV, Specman, test-bench development, HVL, assertions development, eRM methodology, formal verification, constraint randomization

Shell, Pcie, Perl, Arm, Python, Tcl, MCU, AMBA, Axi, UCIe, systemverilog

Tcl, Verilog, Ethernet, Python, Pcie, formal verification, area optimization, FPGA prototyping, systemverilog, Emulation, Rtl Design, micro-architecture, power efficiency, CXL, Timing Closure, high-speed IO protocols, UCIe chiplet interconnects

Linux O.S., System Verilog, Python, Perl, Networking Protocols, Arm Assembly, EDA Verification tools, Object-Oriented Design, Uvm

static timing analysis, Dft, low-power design methodologies, LINT, micro-architecture development, Cadence-based ASIC design environments, SystemVerilog RTL design, formal verification, cdc, Logic Synthesis