automation, Ovm, Tcl Scripting, Perl, Verilog, Specman, SV, assertions development, functional and code coverages, RTL, Uvm, SDF sim debug, GLS, formal verification, eRM methodology, test-bench development, closure constraint randomization, HVL

Pcie, Verilog, Ethernet, Synthesis, cdc, UALink, Simulation, timing considerations, UCIe, systemverilog, LINT, CXL

Perl, Python, Tcl, Xcelium simulation, vManager, Real-Number Modeling, Verilog-AMS, JasperGold, Uvm, SVA, systemverilog

UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), C, C++, Shell, Pcie, Perl, Arm, Python, Tcl, Systemc, MCU, Hardware Emulation Platforms, RISC-V, UCIe, systemverilog, Verification Methodology, AMBA, Axi, Formal Model Equivalence Checking Tools, formal verification, VC Formal

static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog