Unix, Linux, Perl, Shell scripting, Python, Functional Coverage, Assertions SVA, Emulation Platforms, Palladium, Uvm, RTL Debug, systemverilog, ZeBu, Veloce

Debugging, Software testing acceleration, Emulation, Zebu, Veloce, Hardware design validation, Palladium

lauterbach , Spi, C, Systemc, Usb, Shell, Tcl, Verilog, Jtag, Python, Pcie, Perl, DDR, Axi, Coresight, LPDDR, RTL, UltraSoC, Cadence Palladium, systemverilog, VHDL, Cadence Palladium XP, ZeBu

ARM Architecture Cortex-M7, Synopsys Zebu emulators, Logic Analyzer, T32 Debugger

DDR, Pcie, Ethernet, Building complex SOC emulation models, Emulation model development, Memory technologies interfaces, Transactor integration, SOC inter-connect buses, Palladium, Processor Architecture, SOC components, IO protocols, Model bring-up activities, HBM, Zebu, Veloce, CXL

C, Verilog, Gdb, System Verilog, Python, Tcl, Veloce, Zebu, Palladium, waveform debuggers

clocking , Verilog, System Verilog, SOC Emulation, SOC boot flow, Power management flows, Synthesis, PNR, FPGA based prototyping platforms, Low Power Verification, System Verilog Assertions, RTL GLS level simulations, Platform bring up in Emulators or Silicon, Emulation platforms, Functional Verification, Timing Analysis

C, Verilog, Gdb, System Verilog, Python, Tcl, Zebu, Veloce, Palladium, waveform debuggers

Perl, Verilog, Python, Tcl, Cadence Xcelium, Palladium, Rtl Design, Synopsys VCS, VHDL, Zebu, SoC Verification, Velloce

FPGA Design, Python Scripting, Soc Architecture, Test Automation, systemverilog, Verification Methodology, Hardware Debugging, Signal Integrity, Performance Analysis, Emulation Tools