Pli, C, Systemc, perl, Usb, Python, Pcie, Cadence Z3, FPGA prototyping, NVLINK, Xilinx Vivado, Synopsys ZeBu, ProtoCompiler, CHI, Emulators, SV Verilog, dpi, hardware emulation, Siemens Veloce, CPU-GPU coherency, CXL, Simulators, Synplify Premier

Ovm, Verilog, System Verilog, C, Systemc, PERL, Shell script, Assembly Language, dpi, SoC Verification, Uvm, Emulation

bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, hierarchical memory subsystems, Specman E, Debug, IP subsystem SoCs, interconnects, regression systems, congestion control, systemverilog, vector processing units, revision control systems, full verification life cycle, packet processing, constrained-random verification environments, AI ML Accelerators, Verification, standard IP components

Tcl, Python, Perl, systemverilog, Functional Verification, UVM methodology, High-speed networking interfaces, Coverage-driven verification, Ethernet IPs, Emulation platforms or FPGA prototyping

JIRA, Jenkins, Analyzing verification issues, Intel Quartus, Xilinx Vivado, FPGA design and verification following the DO-254 process, Interpreting schematics and layout diagrams, RTL design using VHDL, Electronic components and circuit design flow, Microchip Libero SoC