logic bist , In-System Test (IST), Power-on self-test (POST), Scan Insertion, Multi-voltage power-gated designs, MBIST, Synopsys TestMAX, Scan compression, Siemens Mentor Tessent, DFT architecture, Cadence Modus, ATPG, Hierarchical DFT, Stuck-at, MBIST Memory Built-In Self-Test with repair capabilities, Path Delay, Transition

automation, Scripting, scan compression, BSCAN, MBIST, Siemens Tessent, SSN TestKompress, DFT architecture, ATPG, EDA Tools, Synopsys TetraMAX, DFTMAX, LBIST, IJTAG

logic bist , DFT architecture, Functional BIST, Digital design flows, Scan compression, SoC MCU architecture, DFT protocols

Clp, Perl, Python, Tcl, Scan Insertion, Hybrid-TK Compression, SoC DFT Architecture, ATPG DRC analysis, P1500 implementation, Memory BIST implementation, JTAG BSCAN, MBIST, LEC, Bridging Cell-aware iddq fault models, iJTAG, Stuck at TDF, Logic and DRC analysis, Test coverage debug, ZERO delay and SDF based scan, LPCT, JTAG simulations, power analysis methodologies, LBIST

Dft, MBIST, LBIST, ATPG, Scan Insertion, GLS

occ, Memory-BIST, DFT architecture scan Insertion compression at core level and SoC level, SSN architecture, timing and no-timing simulations, clock architecture, ATPG pattern generation coverage analysis