simulation and verification flow, DFT design and verification, silicon bringup, DFT technologies, fault modeling, ASIC DFT synthesis, IP integration, DFT specification definition, silicon debug activities

logic bist , static timing analysis, UNIX, Jtag, Linux, Perl, Tcl, DFT techniques, Synthesis, Scan Insertion, memory BIST, waveform debugging tools, Verilog simulator, equivalency checking, ATPG, EDA Tools, scan compression architecture, SSN Scan, IEEE standards, c-shell

Logic Design, Static Timing Analysis, Tcl, Python, Perl, Jasper, IR drop, coverage analysis, RTL lint tools, ATE debug, Logic Synthesis, EDA Tools, Sta, RTL2GDS flow, Logic Equivalent Checking, Cadence Modus, Synthesis, post silicon validation, Verification, DFT concepts, ATPG tools, RTL implementation, debugging skills, Scan Insertion

Gate level simulations, Synthesis, Timing Constraints, Logicbist insertion, ATPG, Digital RTL coding, Siemens, Cadence, Mentor, Synopsys, TetraMax

scan chain design and implementation, boundary scan techniques and tools

logic bist , static timing analysis, UNIX, Jtag, Perl, Linux, Tcl, DFT techniques, Synthesis, Scan Insertion, memory BIST, waveform debugging tools, Verilog simulator, equivalency checking, ATPG, EDA Tools, scan compression architecture, IEEE standards, SSN Scan, c-shell