Verilog, Ovm, System Verilog, Synopsys VCS, Cadence IES, VMM, formal property checking tools, Uvm

Noc, Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Scripting, Verdi, IUS, Uvm, GLS, systemverilog, debug tools, Axi, IP SOC verification, Questa, CXL, CPU-based verification

Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm

Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm

Design Verification, Uvm, Verification Planning, systemverilog

C++, Usb, Ethernet, Perl, engineering services, Asic verification

Unix, Shell, Linux, System Verilog, Pcie, VIP coding, Uvm, Python Script, Constraint based Random verification, Test cases coding, Coverage strategies and measurement, Test Plan design, Skill, DDR verification, Digital Design and Verification methodologies

Vcs, Regression Testing, systemverilog, Questa, Uvm, Testbench Development, Verification Plan Creation, Protocol Compliance, Modelsim, Simulation Debugging, formal verification, DDR Verification, Verification Coverage

Ethernet, Python, Perl, Shell, AHB, Uvm, systemverilog, Axi