Usb, DDR, Pcie, Verilog, Ethernet, LINT, Sta, Synthesis, cdc, UCIe, systemverilog, spyglass, VHDL, formal checking, RDC, HBM

Verilog, RDC, LINT, ISO 26262, Safety analysis methodologies, Functional Safety concepts, RTL design and integration, systemverilog, ASIL requirements, Synthesis checks, cdc, Micro-architecture development