Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

Usb, DDR, Perl, Pcie, Ethernet, Python, Tcl, Uvm, coverage-driven verification, systemverilog, digital design RTL understanding, AMBA, MIPI, SVA

Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog

Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage

Cadence Tools, Gate level simulations, VHDL, Formal verification methodologies, VAMS, Testbench creation, Uvm, systemverilog, Motor control for BLDC BSM motor driver devices

Perl, Python, Tcl, DisplayPort, HDMI, MIPI DSI, Uvm, systemverilog

Gpio, DDR, Pcie, Uart, I2c, Spi, UVM methodology, HBM, CXL, QSPI, I3C, systemverilog

Nvme, Pcie, Ethernet, System Verilog, Uvm, Axi, APB, CXL, Industry-standard simulation and debug tools, UCIe, AHB

Vcs, Pcie, Python, Tcl, Xcelium, Uvm, systemverilog, APB, Questa, AXI4, AHB, SVA