Senior Design Verification Engineer
Senior Design Verification Engineer
smartsoc solutions pvt ltd- Posted a month ago
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Job Description
Required Experience
- 5+ years of hands-on ASIC / SoC Design Verification experience
- Strong experience with SystemVerilog & UVM
- Hands-on verification experience in any one or more of the following protocols:
- PCIe / PCI Express
- DDR / LPDDR
- MIPI
- SerDes
- USB
- Ethernet
- CXL
- UCIe
- High-Speed Interconnect / Data Transfer Protocols
Key Responsibilities
- Develop and execute functional verification strategies for complex ASIC/SoC designs.
- Develop SystemVerilog/UVM testbenches, test scenarios and verification environments.
- Create test plans, test cases, functional coverage and assertions.
- Perform debugging and root-cause analysis using simulation and waveform tools.
- Work closely with RTL Design, Architecture and SoC teams to identify and resolve design issues.
- Drive verification from test planning through coverage closure and sign-off.
- Participate in IP, subsystem and SoC-level verification.
More Info
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Key Skills
About Company
Skills:
Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog
Skills:
SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification
Skills:
Cadence Tools, Gate level simulations, VHDL, Formal verification methodologies, VAMS, Testbench creation, Uvm, systemverilog, Motor control for BLDC BSM motor driver devices
Skills:
Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage
Skills:
Vcs, Pcie, Python, Tcl, Xcelium, Uvm, systemverilog, APB, Questa, AXI4, AHB, SVA