Logic Design, Sta, scan BIST, tessent, on-chip scan compression, gate level simulation, Fault Models, automation methods, ATPG, pattern generation, VLSI simulation tools, Fault Simulation

logic bist , Usb, Perl, Pcie, Shell scripting, Static Timing Analysis, Python, Tcl, Memory BIST, Mentor, Cadence, IEEE 1149.1 JTAG, IEEE 1500, Analog Mixed-Signal test structures, DFT architecture, ATPG, EDA Tools, IEEE 1687 IJTAG, Siemens, Synopsys

bist , Jtag, ATPG, Cadence Modus, Synopsys DFTMAX, Scan Insertion, DFT methodologies, Mentor Tessent

bist , Perl, Debugging, Python, Tcl, Logic Design, Sta, RTL, Scan, make, tessent, on-chip scan compression, gate level simulation, Fault Models, automation methods, ATPG, pattern generation, VLSI simulation tools, Fault Simulation

scripting skills in Perl, tessent DFT, DFT architecture definition, HDLs, Genus, Scan, MBIST, Cadence digital implementation tools, Tempus, JTAG boundary scan, ATPG flow implementation

DFT verification, MBIST insertion, EDA Tools, Fault Simulation, Pattern generation

Perl, Python, LINT, Sta, Synthesis, DFT timing, DFT EDA Tool Tessent, LEC, Low Power designs

Shell, Perl, Vcs, ATPG, MBIST, MentorETVerify, Modelsim, TestKompress