rtl development , Perl, Verilog, Python, Tcl, LINT, Synthesis, cdc, SOC design, NoC-based SoC architectures, structural checks, NoC microarchitecture, Timing, RTL quality signoff, ASIC SoC development flows, systemverilog, synthesizable RTL, spyglass, RDC

Verilog, LINT, SDC constraints, cdc, UPF, systemverilog, Rtl Design, RDC, VCLP, Synthesis, SoC integration, Makefile-based flows, Low-power design concepts, Scripting in Tcl