simulation and verification flow, DFT design and verification, silicon bringup, DFT technologies, fault modeling, ASIC DFT synthesis, IP integration, DFT specification definition, silicon debug activities

Dft, Design For Testability, Scan Insertion, Scan Compression, DFT Compiler

boundary scan , bist , Jtag, Debugging, physical design constraints, Sta, verification flows, ATE test pattern generation, compression techniques, MBIST, Analytical Skills, TetraMax, Synopsys DFT Compiler, DFT tools, Tessent, silicon bring-up, Scan ATPG, LBIST, RTL design synthesis

DFT strategies, Fault Simulation, DFT sign-off, scan compression, ATPG pattern generation, JTAG IEEE 1149.1, ATE test program development, IEEE 1687 iJTAG, Scan Insertion