Synthesis, Asic, Rtl Design, Analytical Skill, Problem Solving Skills

power optimization , Cpu, Noc, Tcl, Verilog, Networking, System Verilog, Python, Perl, LINT, Synthesis, High-Level Synthesis, Micro-architecture Development, Peripheral Subsystems, cdc, RTL Coding, Formal Verification Methodology, Timing Closure, Shell-scripting, power analysis

Perl, Python, Tcl, UPF-based flows, constraint development, RTL synthesis, Fusion Compiler, Synopsys Design Compiler, Timing Closure, low-power design methodologies, Cadence Genus

Perl, Python, Tcl, Timing Closure STA, RTL-to-GDSII Execution, Red Hawk, Programming Scripting, Fusion Compiler, LEC, Tempus, Cross-Functional Collaboration, Physical Formal Verification, Calibre, Innovus, primetime, PPA Optimization, EDA Tools, VCLP

Host & Userspace, Rtl Design, Synthesis, ASIC development cycle, ASIC design methodologies, Verification, Infra Silicon Enablement