power optimization , Cpu, Noc, Tcl, Verilog, Networking, System Verilog, Python, Perl, LINT, Synthesis, High-Level Synthesis, Micro-architecture Development, Peripheral Subsystems, cdc, RTL Coding, Formal Verification Methodology, Timing Closure, Shell-scripting, power analysis

Unix, Python, Lsf, Bitbucket, Static timing analysis, AI ML, Jenkins, Git, Linux, Splunk, GenAI, CI CD process, DesignSync, Dft, EDA Tools, ASIC Design, Convolutional Networks, Graph Neural Networks, VLSI CAD, make, reinforcement learning, Design revision control, Design Verification, Power-aware flows

Perl, Static Timing Analysis, Python, Tcl, Timing Closure STA, RTL-to-GDSII Execution, power analysis, Red Hawk, Programming Scripting, Fusion Compiler, Signal Integrity Analysis, Cross-Functional Collaboration, Tempus, LEC, Physical Formal Verification, primetime, Innovus, Calibre, PPA Optimization, EDA Tools, VCLP

pipelining , Ecos, Perl, Python, Tcl, Clock gating, Design DFT, UPF, Low-power design implementation, MCMM synthesis, Physical Synthesis, Multi-clock domain designs, STA timing closure, Netlist delivery, Power optimization flows, Synthesis methodologies, Timing Constraints, Timing constraints validation, formal verification

conformal lec , Python Scripting, Perl, Verilog, Clp, Tcl, Synthesis, DFT Insertion, Low Power Checks

bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Axi, AMBA, Timing Constraints, ATPG, APB, Questa, microcontroller platforms, Cadence Virtuoso, AHB

Version Control Systems, Tcl, Verilog, static timing analysis, Perl, Git, Shell, Perforce, Python, Scripting Languages, AHB, LEC, systemverilog, EDA Tools, LINT, Rtl Design, Synthesis, APB, Axi, SoC Architecture Design, SoC Integration, cdc, formal verification, AMBA protocols, Simulation