Silicon Validation, DDR, Sta, RTL Synthesis, P R Verification, SERDES, ASIC SOC design, MBIST, DFT methodologies, Mixed Signal IPs, Pll, Dft, ATPG, EDA Tools, Scan, manufacturing test flows

logic bist , Usb, Perl, Pcie, Shell scripting, Static Timing Analysis, Python, Tcl, Memory BIST, Mentor, Cadence, IEEE 1149.1 JTAG, IEEE 1500, Analog Mixed-Signal test structures, DFT architecture, ATPG, EDA Tools, IEEE 1687 IJTAG, Siemens, Synopsys

Shell, Perl, Vcs, ATPG, MBIST, MentorETVerify, Modelsim, TestKompress

DFT insertion flows, JTAG 1149.1, IEEE1687, IEEE1500, Cadence tools and flows, SoC ASIC Digital Design, Timing Analysis, Verification of ATPG testbenches, Debug and Analysis of failures, LBIST, scan chain insertion, compression scan insertion, equivalency checks

Tcl, Python, Perl, Scan Architecture, Gate-level Simulation, MBIST, Scan Insertion, ATPG, Scan Compression, DFT Validation, IEEE 1500 standards

test mode timing constraints definition, Genus Synopsys, DFT concepts, Scan Insertion, Transition delay test coverage analysis, TetraMax, simulating test vectors, equivalence check DFT DRC rules, ATPG coverage analysis, Cadence Encounter Test, DFTMax, ASIC DFT, timing fixes

boundary scan , Technical Leadership, Perl, Python, Tcl, test compression, scan compression, DFT signoff, test access strategies, pattern optimization, DFT methodologies, MBIST, DFT architecture definition, Failure Analysis, ATPG, silicon bring-up, yield ramp, LBIST

Verilog, Scan Insertion, ATPG, systemverilog