Lead DFT Engineer
Lead DFT Engineer
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Job Description
Lead DFT Engineer
Location: Bengaluru, India
Experience: 7–12 Years
About the Role
We are looking for a Lead DFT Engineer to drive Design-for-Test implementation for complex SoCs across advanced technology nodes. You will own DFT architecture, implementation, and sign-off with a strong focus on Scan Insertion, MBIST, and ATPG, enabling high-quality silicon with optimal test coverage.
What You'll Do
- Define and implement DFT architecture for complex SoCs and IPs.
- Drive Scan Insertion, scan compression, scan stitching, and scan verification.
- Develop and integrate MBIST solutions for embedded memories and memory repair flows.
- Generate and optimize ATPG patterns for stuck-at, transition, and advanced fault models.
- Perform DFT verification, coverage analysis, pattern validation, and debug.
- Collaborate with RTL, Physical Design, STA, and Test Engineering teams to achieve DFT closure.
- Drive DFT sign-off, improve test coverage, and optimize test time and silicon quality.
- Develop automation scripts to improve DFT productivity and flow efficiency.
What We're Looking For
- 7–12 years of hands-on experience in Design for Test (DFT).
- Strong expertise in Scan Insertion, scan compression, and scan architecture.
- Deep experience with MBIST implementation, integration, and verification.
- Strong knowledge of ATPG generation, fault simulation, and coverage optimization.
- Hands-on experience with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX/DFT Compiler, or equivalent.
- Understanding of JTAG/IEEE 1149.1, boundary scan, and IEEE 1500 standards.
- Experience with DFT validation, gate-level simulation, and scan debug.
- Proficiency in TCL, Python, or Perl scripting for flow automation.
- Excellent debugging, analytical, and cross-functional collaboration skills.
Qualifications
- B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Science, or a related discipline.
Why Join Us
- Own DFT implementation for cutting-edge SoCs built on advanced process technologies.
- Work with world-class silicon teams on high-performance semiconductor products.
- Influence DFT methodology, automation, and next-generation test architectures.
More Info
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Key Skills
About Company
Skills:
bist , boundary scan , Jtag, test compression, ATPG, EDA Tools, Scan Insertion, DFT methodologies, Logic Memory, Synopsys TestMAX, Mentor Tessent
Skills:
MBIST Insertion Verification, ATPG Coverage Analysis Debug, Scan Insertion Compression, Boundary Scan Verification, Mentor Cadence Synopsys Tools
Skills:
Perl, Shell scripting, Scan Insertion, Stuck at Transition ATPG, silicon debug, DFT Silicon bring up expertise, Yield Analysis Debug, Test cost reduction analysis, VCS simulation tool, Scan Architecture, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Synopsys Tetramax, SOC Tape-Outs, Verilog RTL design, DFTMAX, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features
Skills:
scan compression, DFT architecture, ATPG, Scan Insertion, MBIST, Cadence DFT tools, test coverage analysis
Skills:
Dft, ATPG, MBIST, CCS JTAG