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Hiring experienced DFT Engineers - Leading Global semiconductor Design Organization
Experience: 4 to 12 Years
Location: Hyderabad & Bangalore
We are looking for an experienced DFT Engineer to work on next-generation ASIC/SoC designs. The role involves Scan, MBIST, ATPG, DFT implementation, and verification, while collaborating with global engineering teams to deliver robust and high-quality semiconductor solutions.
Key Responsibilities:
Interested Candidate can share their resume at [Confidential Information]
Job ID: 151635793
Skills:
Logic Design, Sta, scan BIST, tessent, on-chip scan compression, gate level simulation, Fault Models, automation methods, ATPG, pattern generation, VLSI simulation tools, Fault Simulation
Skills:
logic bist , Usb, Perl, Pcie, Shell scripting, Static Timing Analysis, Python, Tcl, Memory BIST, Mentor, Cadence, IEEE 1149.1 JTAG, IEEE 1500, Analog Mixed-Signal test structures, DFT architecture, ATPG, EDA Tools, IEEE 1687 IJTAG, Siemens, Synopsys
Skills:
bist , Jtag, ATPG, Cadence Modus, Synopsys DFTMAX, Scan Insertion, DFT methodologies, Mentor Tessent
Skills:
bist , Perl, Debugging, Python, Tcl, Logic Design, Sta, RTL, Scan, make, tessent, on-chip scan compression, gate level simulation, Fault Models, automation methods, ATPG, pattern generation, VLSI simulation tools, Fault Simulation
Skills:
scripting skills in Perl, tessent DFT, DFT architecture definition, HDLs, Genus, Scan, MBIST, Cadence digital implementation tools, Tempus, JTAG boundary scan, ATPG flow implementation