static timing analysis, Synthesis, verification methodologies, design optimization techniques, low-power design methodologies, Power Planning, Place And Route, FC Innovus, Clock Tree Synthesis

C, Routing, Perl, Tcl, Clock Planning, primetime, floorplanning, ICC2, LEC, Calibre, Innovus, Physical Verification, Placement, Timing Closure, Physical Design Implementation, EDA Tools

Python, Tcl, floorplanning, Physical design flows, Logical Equivalence, Clock CTS, Synthesis, Timing Analysis, EDA Tools, Budgeting, Physical Verification DRC LVS ERC, Place And Route

Static Timing, Routing, Physical Verification, Synthesis, Power Efficiency, Custom Clocking, Physical Design, Placement, floorplanning, Formal Equivalency, IR-Drop

redhawk , Tcl, Perl, Python, SDC, Foundry PDKs, Implementation tool suite, EDA Tools, Power gating, Cadence, primetime, Tempus, Synopsys ICC2, CPF, Timing Analysis, TSMC, Physical Design, Synopsys, UPF, Cadence Innovus, Sta, Multi-voltage domains, Voltus, Signoff tools, Samsung, Low-power design techniques

Debugging, Perl scripting, Cadence Tools, IP QA, Mentor Calibre, CMOS circuit design fundamentals, Innovus, RTL2GDS, CMOS layouts, Apache RedHawk, Genus, Synopsys Prime Time

ICV or Calibre tools, block subsystem timing closure, physical design verification, full chip floor-planning and integration, IR EM analysis and resolution, block level and full-chip physical verification methodology, block physical design PDV and IR