Linux, Perl, Verilog, Python, Tcl, iJTAG, Dft, ATPG, Scan, MBIST

Verilog, Jtag, Dft, MBIST, IEEE1500, IEEE1687, ATPG, Cadence

Tcl, Verilog, Python, Jasper, Perl, Scan Insertion, VHDL, Memory Test methodologies, ATPG, Xcelium, Genus, Modus

bist , Perl, Debugging, Python, Tcl, Logic Design, Sta, RTL, Scan, make, tessent, on-chip scan compression, gate level simulation, Fault Models, automation methods, ATPG, pattern generation, VLSI simulation tools, Fault Simulation

Logic Design, Tcl, Python, Perl, Mentor, MBIST OCC validation flows, Synopsys, Digital Circuit Design, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, SpyGlass DFT rules, Sta, Cadence, Physical design flows, SSN design and IEEE 1687 IJTAG standards, RTL design synthesis

boundary scan , memory test , Digital Logic Design, Jtag, static timing analysis, Hdl, compression techniques, reliability tests, IEEE1149.1, Gates verification, silicon bring-up, test clocking, ASIC Logic Design Flow, Scan ATPG, IDDQ, HTOL, ATPG configurations, BIST architecture, DFX verification, Eco, Simulation

Logic Design, Synopsys, MBIST OCC validation flows, IEEE 1687 IJTAG standards, Digital Circuit Design, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, SpyGlass DFT rules, Mentor, Sta, Cadence, DFT for complex ASIC SoC designs, SSN design, Physical design flows, RTL design synthesis