C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

ASIC design flow, C Assertions coding, ARM based SOC software framework, Analog-Digital Interface, WREAL AMS model, SV-UVM, UVM assertion based coverage driven verification, constraint random test generation, multi-core multi-layer APIs, functional coverage, ARM processor based SoC architecture, ASIC verification methodologies

Automotive Safety Integrity Levels (ASIL), C, System Verilog, Python, C++, Debugging, Vc, Perl, Systemc, VPlan, ARM bus protocols, Logic Memory power collapse, HW-SW debug, Silicon debug tool chains, Formal, Scoreboards, Virtual Memory concepts, Certitude, Sequencers, UVM based verification, SoC system architecture, Analytical and problem-solving skills, Dynamic clock gating, Monitors

clocking , Verilog, System Verilog, SOC Emulation, SOC boot flow, Power management flows, Synthesis, PNR, FPGA based prototyping platforms, Low Power Verification, System Verilog Assertions, RTL GLS level simulations, Platform bring up in Emulators or Silicon, Emulation platforms, Functional Verification, Timing Analysis