Shell, C, Perl, Verilog, Python, Tcl, EDA Tools, UVM methodology, systemverilog

power optimization , Noc, Networking, Cpu, Perl, Verilog, System Verilog, Python, Tcl, LINT, High-Level Synthesis, cdc, power analysis, Peripheral Subsystems, Formal Verification Methodology, Shell-scripting, Synthesis, Timing Closure, RTL Coding, Micro-architecture Development

Hard IP integration, Clock and Power distribution, STA setup convergence methodology, Power Integrity Analysis, Hierarchical design implementation, Automation scripts within STA tools, Timing Closure, Timing ECO Implementation strategy, Floor Planning, Debugging skills in implementation issues, ASIC Physical implementation, Global signal planning, Physical convergence, Tweaker Primetime based ECO flows

Perl, Verilog, Python

random testing , Oops, Pcie, Verilog, Debugging, System Verilog, FPGA verification, coverage assertions, Ethernet based protocols, Otn, VCS simulation flow, Uvm, VMM, AXI memory controllers, adversarial testing