Logic Design, Perl, Python, DFT Engineering, SV, coverage metrics, Profiling Tools, Uvm, X prop, Post Silicon Testing, constrained random testing, Architecture Verification

scripting skills in Perl, tessent DFT, DFT architecture definition, HDLs, Genus, Scan, MBIST, Cadence digital implementation tools, Tempus, JTAG boundary scan, ATPG flow implementation

Test Execution, Perl, Python, SV, DFT Engineering, Pre-Silicon Simulation, Uvm, Verification methodologies, Post Silicon Testing, High Speed IOs, Debug, Automation flow development

Debugging, occ, ICL, Dft, DRC coverage, pdl, Scan ATPG, Simulation, IJTAG, SSN

Verilog, Jtag, Dft, MBIST, IEEE1500, IEEE1687, ATPG, Cadence