Perl, Python, Tcl, Clock domain partitioning, Power integrity and power-aware physical implementation, Block and subsystem-level physical design flows, primetime, Fusion Compiler, Clock gating, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Tcl, Shell scripting, Python, Fc, Innovous, Tempus, primetime

Perl, Python, Tcl, Sta, Physical Design, ASIC Implementation, EM, Ir, PDN, make

clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, PNR Floor Plan, Power Mesh, Timing Signoff

Multi-voltage domains, Physical design methodologies, Physical Verification, Power gating, PDN IR signoff, ASIC design flows, DDR PD expertise, 3DIC, Physical Design, Bump Spec understanding, RDL-design, PPA optimization, PCIE-high speed interface