power optimization , Scripting, Perl, Python, Tcl, Mentor, Cadence, Physical design flows, EDA Tools, Synopsys, Signal Integrity, Timing Analysis

Static Timing, Routing, Physical Verification, Synthesis, Power Efficiency, Custom Clocking, Physical Design, floorplanning, Placement, Formal Equivalency, IR-Drop

primetime, Physical Design, PPA Optimization, RTL Co-Optimization, Synopsys Fusion Compiler, Cadence Innovus, Tempus, EDA Tools

redhawk , Python Scripting, Shell, Perl, Verilog, Tcl, full-chip aspects, Fusion compiler, Formal equivalence, PTPX, ICC2, signoff, IP integration, Timing Verification, Physical Design, primetime, timing convergence, VHDL, PNR, Low Power Checks, EDA Tools

micro architecture , sign-off convergence, low-power physical design, RTL, electrical checks, ASIC design implementation, Physical Verification, CPU implementation

power integrity , Routing, Perl, Python, Tcl, Chip finishing, Metal fill, Clock Trees, Tapeout checks, Physical Verification, Sealring, Signal Integrity, RTL2GDS flow, Floorplans, Power Distribution Network, Physical Design, Timing Closure, Placement, Physical Sign off, Equivalence Check, Synthesis Constraints

Scripting, Python, Routing, Tcl, CTS, primetime, 3D IC, ICC2, Cadence, LVS, IR Drop, Calibre, Innovus, Physical Verification, HBM, Placement, Si, Chiplets, floorplanning, EM, Full-Chip Physical Design, Advanced Packaging, Timing Closure, DRC, Advanced nodes 7nm or below, 2.5D, EDA Tools, Synopsys

redhawk , Tcl, Perl, Deep sub-micron designs, Dc, Synthesis, Timing Closure, Pt, LVS, ICC, VSLP, Logic equivalence checking, Low Power checking, Calibre, STA timing, Formality, Place And Route, DRC, Physical Design, SOC design