Uncore subsystems, Physical Design, FinFET nodes, EDA suites, Cadence, Synopsys, RTL-to-GDSII

Perl, Python, Tcl, primetime, Cadence Innovus, EM analysis, Physical Verification, Signal Integrity, StarRC, Timing Closure, low-power design techniques, Synopsys ICC2

Routing, Sta, CTS, PNR, Physical Design, floorplanning, Timing Closure, Placement, Sign-off

Low Power SoCs, Physical Verification, Physical Design, Timing Closure, Floor Planning, Dynamic IR Drop, Package Co-design, Place And Route, Clock Tree Synthesis, IO Planning, Power Grid Design

Rtl Design, Synthesis, RISC CPU IP, Emulation, silicon bring-up, Microarchitecture, Verification, Timing Analysis, Physical Design, SoC design methodology

power integrity , Perl, Python, Tcl, physical design sign-off, static dynamic IR drop, physical ECOs, Cadence Voltus, electromigration, power-grid optimization, PG strengthening, Ansys RedHawk, EM IR analysis, vectorless EM IR analysis