DDR, Pcie, Verilog, Ethernet, Python, Cadence Incisive, UCIe, Uvm, Synopsys VCS, formal verification, VHDL, Modelsim

performance verification of ASICs, ASIC standard interfaces, verification components, formal tools, Design Verification, assertion-based verification, Uvm, systemverilog, memory system architecture

Analog and mixed signal electronic parts, Software simulations, Design Verification, Integrated circuitry

Pcie, Ovm, Axi, AMBA, CHI, Ace, interconnect and bus protocols, cache coherency concepts, CXL, Uvm, systemverilog

Vcs, Shell, Perl, Python, PCIe Gen5, Xcelium, Uvm, systemverilog, AMBA, Axi, APB, Questa, CXL, AHB, SVA

analog circuits , Fpga, Logic Design, Verilog, Micro-architecture, Synthesis, Uvm, Timing Constraints, Regression frameworks, Power product design, System-Verilog, Functional Verification, RTL Coding, Sta, Synthesis scripts, ATPG generation, Scan Insertion, formal verification, ABV, Timing Analysis, Digital Verification

Spi, I2c, Uart, Pcie, Usb, Noc, cdc, SoC IP Design, AMBA protocols, Network on Chip

Spi, I2c, Gpio, Uart, Pcie, DDR, UVM methodology, I3C, QSPI, CXL, systemverilog, HBM