layout verification , Computer Engineering, System Verilog, Tcl, low-power designs, Electrical Engineering, Computer Science, design rules, Vlsi Design

power integrity , Routing, floorplanning, Crosstalk Analysis, Timing Optimization, Cadence Innovus, LVS, ECO Engineering Change Order, Signal Integrity Closure, Physical Verification, Physical Design, DRC, EMIR Analysis

Tcl, Python, PERL, Seahawk, Tempus, primetime, Innovus, ICC2

power optimization , Perl, Python, Scripting, Tcl, Mentor, Timing Analysis, Cadence, Physical Design, Signal Integrity, EDA Tools, Synopsys

redhawk , Tcl, Routing, Python, Perl, Multi-voltage domains, Foundry PDKs, UPF, Timing Closure, Signoff, Cadence Innovus, Power gating, floorplanning, primetime, Tempus, Synopsys ICC2, CPF, Voltus, Placement, Physical Design, Samsung, Low-power design techniques

Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology