Senior Physical Design Engineer

ACL Digital is Hiring: Senior Physical Design (PD) Engineer

Job Description:

Role: Physical Design Engineer

Location: Bangalore (Onsite)

Experience: 8+ years

Notice Period: 15 days or less

Job Responsibilities:

• Drive the Physical Design (PD) implementation from RTL to GDSII, focusing on high-performance block-level and full-chip designs.
• Lead floorplanning, power grid planning, placement, Clock Tree Synthesis (CTS), routing, and physical verification (DRC/LVS) for advanced process nodes.
• Utilize Cadence Innovus extensively for place-and-route (PnR) and congestion management.
• Perform Static Timing Analysis (STA), crosstalk analysis, and signal integrity closure to ensure robust timing signoff.
• Collaborate with cross-functional teams to resolve complex design challenges related to Power, Performance, and Area (PPA).
• Work on ECO (Engineering Change Order) implementation, timing optimization, and power integrity (EMIR) analysis.
• Mentor and provide technical guidance to junior team members, ensuring high-quality design deliverables.

Key Requirements:

• Education: B.E./B.Tech or M.E./M.Tech in Electronics/VLSI.
• Experience: 8+ years of relevant industry experience in physical design.
• Mandatory Skills: Strong hands-on proficiency in Cadence Innovus is a must.
• Technical Expertise: Experience in floorplanning, CTS, routing, timing closure, and physical verification.
• Advanced Nodes: Proven experience working on advanced technology nodes (e.g., 7nm, 5nm, 3nm).
• Availability: Must be able to join within 15 days or be available immediately.
• Soft Skills: Excellent problem-solving, analytical skills, and the ability to work independently or as part of a team.

Interested can share your resume at: [Confidential Information]