Perl, Python, Tcl, Emulation, systemverilog, System Verilog Assertions

Python, Tcl, Low power or processor designs, Toplevel physical implementation

power analysis, Advanced process nodes, Power Estimation, Power Budgeting, AMBA protocols, Low Power design and implementation techniques, Power-aware design flows, ARM-based SoC architectures, Post Si power measurement analysis and debug, Power management controllers, UPF CPF standards, Clock reset architecture

C, Perl, Verilog, Python, Tcl, Palladium, Hybrid Simulation, Uvm, systemverilog, Emulation, Zebu, Veloce

Cache, Soc Architecture, Verilog, power analysis, Synthesis, memory compression, FPGA design verification, digital logic design principles, systemverilog, logic synthesis techniques, RTL design concepts, FPGA and emulation platforms, Dft, fabric coherence, DRAM, low-power design techniques, assertion-based formal verification

static timing analysis, Verilog, Debugging, Integration, Synthesis, multi-clock domain architectures, digital design fundamentals, power optimization techniques, low-power design methodologies, micro-architecture development, Physical Design, systemverilog, Dft, Axi, APB, Timing Closure, RTL Coding, Verification, AHB

Verilog, Asynchronous interface, Synthesis, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Multi Clock designs, System-Verilog, formal verification

Verification Methodologies, NVME architecture, PCIe transport and link layers, Post silicon debug, SoC Verification, C based SoC verification, Simulation, Testbench architecture, Pattern generation