Github, C, static timing analysis, Silicon Validation, Git, Perl, Verilog, Python, RTL implementation, Synthesis, SOC design, Simulation, assertion-based verification, systemverilog, Cadence EDA tools, formal verification, ASIC Design

rtl verification , Verilog, reset strategy, SoC design flow, Simulation, timing considerations, datapath design, systemverilog, FSM design, Rtl Design, Axi, APB, debugging methodologies, BUS Protocols, AHB, clock-domain handling

ASIC design flow, Standard bus protocols, DFT concepts, Verilog Hdl, Synthesis timing analysis, Cadence, Peripheral interface design, AMBA, Axi, APB, EDA Tools, DMA, Bus systems, Low-power design methodologies, Synopsys, AHB, Cache architectures

rtl verification , Verilog, AHB, SoC design flow, debugging methodologies, systemverilog, datapath design, reset strategy, Rtl Design, clock-domain handling, timing considerations, FSM design, APB, Axi, BUS Protocols, Simulation

UNIX, Linux, Bash, Tcl, Physical Verification, Detailed routing, Cadence, Placement, EDA Tools, Siemens, Clock Tree Synthesis, Synopsys, formal verification, Timing Analysis

C, Ovm, Perl, Verilog, Shell scripting, Arm, Python, Tcl, Systemc, assembly coding, RISC-V, assertion-based verification, Uvm, systemverilog, hardware-software co-verification methodology, MIPI, AMBA, AXI bus protocols, DSP cores, APB, Semiformal Verification, AHB

UNIX, Linux, Bash, Tcl, Physical Verification, Detailed routing, Cadence, Placement, EDA Tools, Siemens, Clock Tree Synthesis, Synopsys, formal verification, Timing Analysis