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Senior RTL Design Engineer

AMD Ventures
Hyderabad, India

Skills:

Perl, Verilog, Shell scripting, LINT, cdc, RTL quality checks, Connectivity, SOC design, VCLP

Early Applicant

Senior ASIC RTL Design Engineer

MosChip Semiconductor
Hyderabad, India

Skills:

Verilog, Asynchronous interface, Synthesis, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Multi Clock designs, System-Verilog, formal verification

Early Applicant

FPGA RTL Design Engineer

epergne solutions
Hyderabad, India

Skills:

Debugging, System Verilog, Sta, Synthesis, Wi-Fi, FPGA RTL design, Uvm, DSP fundamentals, Wireless Communication, 5G, VHDL, high-speed packet processing, AMD Zynq RFSoC, Timing Closure, 5G LTE, Altera Agilex

Early Applicant

Senior RTL Design Engineer

Inotec AMD
Hyderabad, India

Skills:

Perl, Verilog, Shell scripting, LINT, cdc, Connectivity, RTL quality checks, SOC design, VCLP

Early Applicant

Senior RTL Design Engineer

AMD Telecom
Hyderabad, India

Skills:

Perl, Verilog, Shell scripting, LINT, cdc, RTL quality checks, Connectivity, SOC design, VCLP

Early Applicant

RTL Design Engineer

Xilinx
X
Hyderabad, India

Skills:

Shell scripting, Tcp Ip, Ethernet, Pcie, Perl, DMAs, Design for Test methodologies, NVMe based Storage IP, Verilog RTL design, RDMA IPs, VCS simulation tool, Silicon IP development process methodologies

Early Applicant

Senior RTL Design Engineer

AMD Maquinaria
Hyderabad, India

Skills:

Perl, Verilog, Shell scripting, LINT, cdc, RTL quality checks, Connectivity, SOC design, VCLP

Early Applicant
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