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RTL Design Engineer

Inotec AMD
Hyderabad, India

Skills:

arm architecture , PERL, Python, Tcl, cdc, SoC level design integration, LINT, Digital Design, timing exceptions, CHI protocol, writing UPF, Timing Constraints, design reuse, automation using scripting techniques, RTL Coding, designing with multiple power domains

RTL Design Engineer

AMD Telecom
Hyderabad, India

Skills:

arm architecture , PERL, Python, Tcl, cdc, SoC level design integration, LINT, Digital Design, timing exceptions, CHI protocol, Timing Constraints, writing UPF, design reuse, automation using scripting techniques, RTL Coding, designing with multiple power domains

Early Applicant

RTL Design Engineer - SOC Integration

AMD Maquinaria
Hyderabad, India

Skills:

Linux Environment, Perl, Version Control Systems, Verilog, System Verilog, Python, Tcl, SOC tools, DFT technologies, UPF, Rtl Design, primetime, spyglass, Cadence Conformal, Synopsys Design Compiler, Questa CDC, VCS simulation

Early Applicant

RTL Design Engineer

ALTEN Calsoft Labs
Hyderabad, India

Skills:

Verilog, Soc, Timing Closure, IP integration, Synthesis, linting, systemverilog, ASIC, Digital Design, gate-level simulations

Early Applicant

RTL Design Engineer - SOC Integration

AMD Ventures
Hyderabad, India

Skills:

Linux Environment, Perl, Version Control Systems, Verilog, System Verilog, Python, Tcl, SOC tools, DFT technologies, UPF, Rtl Design, primetime, spyglass, Cadence Conformal, Synopsys Design Compiler, Questa CDC, VCS simulation

Early Applicant
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