Makefile, Windows, Linux, Perl, Python, IP-level ASIC verification, simulation profiling, UVM methodology, UVM testbenches, systemverilog, formal verification, Efficiency Improvement, UVM-based verification frameworks

traceability , Requirements Management, Technical Documentation, Cmmi, Subsystems integration, SoC design methodologies, cdc, power management, Security IP, Interconnects, LINT, SoC RTL Integration, Clocking Reset Core, Functional Safety, SoC u-Architecture, IP Integration reviews, express Synthesis, Verification smokesuite, RDC signoffs, IS026262, BE reports reviews, Debug Trace

Verilog, Digital Logic Design, System Verilog, analog IC design methods

Makefile, Windows, Linux, Perl, Python, IP-level ASIC verification, simulation profiling, UVM methodology, UVM testbenches, systemverilog, formal verification, Efficiency Improvement, UVM-based verification frameworks

DDR, Pcie, System Verilog, HBM, Uvm, UCIe

Makefile, Windows, Perl, Linux, Python, IP-level ASIC verification, simulation profiling, UVM methodology, UVM testbenches, systemverilog, formal verification, UVM-based verification frameworks

Makefile, Windows, Shell, Linux, Python, IP-level ASIC verification, simulation profiling, UVM methodology, UVM testbenches, debugging RTL code, systemverilog, acceleration, formal verification, testbenches, Efficiency Improvement, UVM-based verification frameworks

Verilog, clock tree, Hspice, Fuse Logic, analog and digital voltage readouts, synchronous design, MBIST, circuit simulations, Test Mode Logic, DFT circuits, FINESIM