static timing analysis, Verilog, Python, Tcl, SDC development, Tempus, Cadence Innovus, simulation methodologies, Rtl Design, transistor-level concepts, Genus, digital circuit operation, custom layout fundamentals, place-and-route, multi-clock designs, Synthesis, digital design fundamentals, floorplanning, Physical Verification, systemverilog, CDC concepts, Timing Constraints, Liberty timing models, characterization concepts

Verilog RTL coding, spyglass, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, multi-domain clock synchronization, high performance memory subsystems, ASIC debugging

Computer Architecture, Perl, Debugging, Python, Formal Verification methodologies, IP SOC verification, Functional Verification, Uvm, systemverilog, Rtl Design

wireless protocols , modem, System Verilog, Wifi Standards, constraint random tests, assertion coverage-based verification methodology, debugging RTL TB issues using Verdi, Uvm, formal static verification methodologies

System Verilog, Digital-analog interface requirements, RTL design and development, Linting, Mixed-signal design flows, RDC analysis, Coverage-driven design methodologies, Timing Constraints, Digital control logic, Synthesis and timing closure methodologies, RTL coding in Verilog, Low-power design techniques

Digital Logic Design, Verilog, System Verilog, analog IC design methods