power optimization , Noc, Networking, Cpu, Perl, Verilog, System Verilog, Python, Tcl, LINT, High-Level Synthesis, cdc, power analysis, Peripheral Subsystems, Formal Verification Methodology, Shell-scripting, Synthesis, Timing Closure, RTL Coding, Micro-architecture Development

Perl, Python, Tcl, Emulation, systemverilog, System Verilog Assertions

Linux, Perl, Python, Tcl, EM, LVS, IR analysis, Calibre, physical signoff flows, ERC, DRC, Parasitic Extraction, Cadence Virtuoso

Perl, Verilog, Python

Red Hat, Bash, Dns, Ldap, Linux Administration, Ubuntu, Iso 27001, Ansible, Centos, Oracle, Python, Security frameworks, CIS benchmarks

C, DDR, Pcie, Memory Consistency Models, verification components, Clock and Power Controllers, Caches, Coherency, Uvm, Security, systemverilog, Packet Processors, Hierarchies, standard verification methodology, LPDDR, Interconnect Protocols

Vcs, Gdb, Shell, Perl, Verilog, Python, ASIC design flow, floor-planning, Timing Analysis, Rtl Design, Eco, Debussy, bring-up lab debug

synopsys primetime , Python Scripting, Design Compiler, SDC constraint authoring and management, Physical-aware synthesis flows, Fusion Compiler, Formality, Physical-Aware Synthesis, STA PrimeTime