power optimization , Noc, Networking, Cpu, Perl, Verilog, System Verilog, Python, Tcl, LINT, High-Level Synthesis, cdc, power analysis, Peripheral Subsystems, Formal Verification Methodology, Shell-scripting, Synthesis, Timing Closure, RTL Coding, Micro-architecture Development

Perl, Python, Tcl, Emulation, systemverilog, System Verilog Assertions

Perl, Verilog, Python

Vcs, Gdb, Shell, Perl, Verilog, Python, ASIC design flow, floor-planning, Timing Analysis, Rtl Design, Eco, Debussy, bring-up lab debug

synopsys primetime , Python Scripting, Design Compiler, SDC constraint authoring and management, Physical-aware synthesis flows, Fusion Compiler, Formality, Physical-Aware Synthesis, STA PrimeTime

Perl, Vcs, Shell scripting, Python, NC, Uvm, systemverilog