Debugging, Scripting, formal verification, assertions, hardware micro-architecture, testplans

Verilog, Debugging, Automation Scripting, formal verification, AI-assisted Workflows, Protocol Verification, Property Checking, SVA, systemverilog, Equivalence Checking, Formal Analysis

Python, Jasper VC Formal, formal verification, Property-based FV, Formal Tools, SVA, Questa Formal

Shell, Python, Perl, formal verification technologies, complexity reduction techniques, high quality testplans, formal testbenches, root-causing counter-examples

Tcl, Perl, JasperGold, digital design concepts, Questa, VC Formal, systemverilog, debugging complex design bugs, convergence techniques, formal coverage metrics, RTL coding in Verilog, Formal OneSpin, formal verification, formal property specification

Verilog, Formal Abstraction Techniques, VHDL, JasperGold, formal verification, VC Formal, systemverilog, Object-oriented Programming