Vcs, Jtag, Pcie, Awk, I2c, Python, Jasper, Sed, Perl, Networking Protocols, Ethernet, PLLs, Uvm, Co-Simulations, GLS, AXI4.0, Verdi, debugs, Emulation Platforms, Test Bench Accelerators, Coverage Driven Methodology, systemverilog, Ate, HW SW Flow

code coverage , Vcs, Perl, Shell scripting, Python, Tcl, NC Xcelium, Asic verification, Uvm, systemverilog, constrained-random verification, functional coverage

C++, Soc, Communication engineering, Simulation, Asic verification, Uvm

Jtag, Verilog, Debugging functional and toggle coverage, CHI, DFT concepts, System Level Testing, Uvm, systemverilog, Axi, lbist, APB, Predictive In Field Testing, MBIST

System Verilog, MPHY, UFS, Unipro, Asic verification, Uvm

Usb, C, Uart, Bash, Spi, Pcie, Perl, Verilog, I2c, Test Plan Creation, Python, System Verilog, Tcl, gate-level simulations, verification methodology, i2s, Uvm, DP, Sd, Test Development, test-bench development, Gate Level Power-Aware simulations, test coverage assessment

Design Verification, ASIC Design, Verification Planning, systemverilog, Rtl Design