Perl, Vcs, Python, Tcl, ASIC Verification using SystemVerilog, NC, Uvm

random testing , Oops, Pcie, Verilog, Debugging, System Verilog, FPGA verification, coverage assertions, Ethernet based protocols, Otn, VCS simulation flow, Uvm, VMM, AXI memory controllers, adversarial testing

Verilog, Jtag, CHI, Uvm, System Level Testing, Debugging functional and toggle coverage, systemverilog, DFT concepts, APB, Axi, lbist, MBIST

System Verilog, MPHY, UFS, Unipro, Asic verification, Uvm

Perl, Python, Tcl, Emulation, systemverilog, System Verilog Assertions

C, DDR, Pcie, Memory Consistency Models, verification components, Clock and Power Controllers, Caches, Coherency, Uvm, Security, systemverilog, Packet Processors, Hierarchies, standard verification methodology, LPDDR, Interconnect Protocols

C, Perl, Verilog, Python, Tcl, Palladium, Hybrid Simulation, Uvm, systemverilog, Emulation, Zebu, Veloce