conformal lec , Unix, Clp, Linux, Tcl, Python, Perl, Cadence Genus, UPF, LEC, IEEE 1801, CPF-based power intent, low-power verification flows, ASIC synthesis

display , simulations , Usb, Pcie, Timing Constraints, UCIe, Verilog Coding, LINT, RTL checks, data path designs, cdc, Rtl Design, Verilog testbench, MIPI, synthesis flow, SDC, DPHY, HDMI

Synthesis, PNR, Timing Closure, Pv, EM-IR Signoff

Tableau, Tcl, Powerbi, Ms Excel, Python, PERL, Ccsp, Sta, AOCV, EDA development, Layout Design, FinFET technologies, Standard Cell Circuit Design, RTL2GDS flow, NLDM, Circuit and MC simulations, LVF, characterization, PNR, Layout Dependent Effects, Skill, CCSN