SDF, automation, Ovm, Tcl Scripting, Verilog, Perl, GLS, Uvm, SV, RTL, Specman, test-bench development, HVL, sim debug, closure constraint randomization, functional and code coverages, assertions development, eRM methodology, formal verification

automation, Ovm, Tcl Scripting, Verilog, Perl, RTL, GLS, Uvm, SV, Specman, SDF sim debug, test-bench development, HVL, functional and code coverages, closure constraint randomization, assertions development, eRM methodology, formal verification

CAD software, Material Selection, Sheet Metal Design, Thermodynamics, Design for Excellence principles, flow analysis, manufacturing methods

Functional Design, Problem Solving, Design For Safety and Reliability, Mechanical Design, Electromechanical Engineering, Computer Aided Design, Electrical Safety

redhawk , Shell, Tcl, Verilog, PERL, Innovus, floorplan exploration and optimization, Starrcxt, place and route methodologies, physical implementation and analysis tools, Fusion Compiler, power integrity and reliability analysis, Calibre, VHDL, low power physical design flows and methodologies, timing and signal integrity analysis, metal-only ECO implementation, power grid planning and implementation, timing optimization and timing closure, placement and optimization, Clock Tree Synthesis

Python, Tcl, primetime, StarRC, ICC2, DSO.ai, Synopsys Fusion Compiler