Digital Logic Design, SOC integration, Micro-architecture design, Rtl Design

Python Scripting, ASIC design flow, Circuit timing STA, C embedded experience, Digital Design, Low power digital design and analysis, RTL design in Verilog SystemVerilog, ASIC design in sub-20nm technology nodes, PrimeTime or equivalent tools

Digital Logic Design, Micro-architecture design, RTL quality checks, SOC Integration, Rtl Design

Python Scripting, Git, PrimeTime or equivalent tools, Modern SOC tools including Spyglass, Version control systems such as Perforce, ASIC design flow, Low power digital design and analysis, Digital Design, C embedded experience, VCS simulation, Cadence Conformal, ICManage, ASIC design in sub-20nm technology nodes, Questa CDC, RTL design in Verilog, Circuit timing STA

Python Scripting, PrimeTime or equivalent tools, ASIC design flow, ASIC design in sub-20nm technology nodes, Low power digital design and analysis, Digital Design, C embedded experience, Circuit timing STA, RTL design in Verilog SystemVerilog

Unix, Python, Shell, Linux, Skill, SoC Integration, Rtl Design

Verilog, Uvm, Synopsys VCS, VHDL, RTL design methodologies, Modelsim, Cadence Incisive