Python Scripting, Analog Circuit Design, Mixed-Signal Circuit Design, virtuoso, ADE XL, SPICE simulators, Post-Silicon Bring-Up

Mixed-signal circuit design, PPA tradeoffs, Memory Cell Design, PLL clock-generation, Layout collaboration, Charge Pumps, Transistor-level design simulation, Clock buffers, Analog Design, Loop Filters

bandgap references , IC level issues, IC development flow, ESD LU, Silicon debugs, High speed level shifters, Design extraction and simulation flows, Temperature Sensor, Switch Cap circuits, Analog feedback loops, Analog Circuit Design, Analog Buffers, Source-Sink LDOs, Ultra-low power Oscillators, Op-Amps, Simulation and Verification, Analog layouts, LDOs, Current Sense SAR ADCs, Charge Pumps, Control Loops, Control loop architectures, Comparators

DFE, Duty Cycle Correction, BGR, Oscillators, High-speed clock distribution, Rx CDR, Tx Serializer Output Driver, CTLE, Generic Analog Circuits, Analog Circuit Design, EDA Tools, Bias Circuits, Deserializer, Circuit design simulation and analysis, LDO, Lower Nodes Experience, Amplifiers, VGA, Comparators, Power Management Circuits, High-Speed SerDes Tx and Rx blocks

chip top-level ownership, Virtuoso Cadence, reliability simulations, silicon debug expertise, Analog Circuit Design

circuit testing , Analog Electronics, analog fundamentals, clocking circuits, analog power circuits, LDO, CMOS technologies, analog behavior modeling, Circuit Simulation, analog to digital converters

Full product development cycle, Quality requirements for automotive products, power management, CMOS BCD Analog Circuits

Layout considerations for advanced nodes 28nm, Voltage regulators, Oscillators, Embedded flash memory design, device physics, Memory interfaces, Analog mixed-signal circuit design, Operational amplifiers, Current mirrors, SPICE extraction tools, process technology, Sense amplifiers, Scripting languages such as PERL, Cadence Virtuoso, LDOs, NVM embedded flash operation, Charge pumps