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Showing 8 jobs
Skills:
Perl, Verilog, Python, Tcl, power analysis optimization, power gating, Simulation, clock gating, systemverilog, UPF CPF methodologies, DVFS implementation, low-power checking tools, formal verification, RTL gate-level and physical design, EDA Tools, low-power design techniques, low-power verification flows, power performance and area PPA targets, multi-voltage
Skills:
clock distribution , Clp, PERL, Tcl, low power design, Sta, PERC, Signal Integrity Analysis, LVS, LEC flow, Tape Out, IP integration, Dfm, Timing Closure, Physical Verification, Synthesis, Gds, Tk, cpf, Clock Tree Synthesis, upf, PNR, Physical Design, ERC, DRC, Floorplan
Skills:
PnR-Floorplan Macro placement, EM IR understanding and fixes, STA analysis, Util area reduction experiments, ECO cycle, Density Congestion Timing issues and fixes on lower tech nodes 5nm, Physical aware Synthesis using FC, PV closure
Skills:
hardware engineering , Perl Scripting, Sta, Circuit Level Comprehension, Low Power Flow, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, IC design, Verification, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Constraints Validation, High Frequency Design, Power Gating, PDN Methodology, PPA Targets, Timing Signoff
Skills:
Debugging, Logic Design, Sta, Circuit Design, Physical Verification, PNR, Physical Design, EDA Tools, Optimization, Rtl Design
Skills:
Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology
Skills:
Tcl, Python, PERL, Seahawk, Synthesis, ECO Timing Closure, Layout Closure, Block-level and Full-chip Floor-planning, primetime, Physical Verification, Ir, CTS, Innovus, Sta, ICC2, Physical Design, Tempus, RTL2GDSII flow, Place And Route, Timing Convergence, High Frequency Design Methodologies
Skills:
Routing, Physical Design Methodologies, Tcl tool scripting, RTL-to-GDSII implementation, DDR design knowledge, primetime, Placement, Calibre, Genus, Innovus, floorplanning, MultiTap-CTS
