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Bengaluru, India

Skills:

PerlVerilogPythonTclpower analysis optimizationpower gatingSimulationclock gatingsystemverilogUPF CPF methodologiesDVFS implementationlow-power checking toolsformal verificationRTL gate-level and physical designEDA Toolslow-power design techniqueslow-power verification flowspower performance and area PPA targetsmulti-voltage

Bengaluru, India

Skills:

clock distribution ClpPERLTcllow power designStaPERCSignal Integrity AnalysisLVSLEC flowTape OutIP integrationDfmTiming ClosurePhysical VerificationSynthesisGdsTkcpfClock Tree SynthesisupfPNRPhysical DesignERCDRCFloorplan

Early Applicant
Bengaluru, India

Skills:

PnR-Floorplan Macro placementEM IR understanding and fixesSTA analysisUtil area reduction experimentsECO cycleDensity Congestion Timing issues and fixes on lower tech nodes 5nmPhysical aware Synthesis using FCPV closure

Early Applicant
Bengaluru, India

Skills:

hardware engineering Perl ScriptingStaCircuit Level ComprehensionLow Power FlowRTL to GDSII ImplementationLeakage PowerSignal IntegrityMulti-Vt FlowIC designVerificationDfmPower Supply ManagementDeep Sub-Micron DesignPhysical DesignConstraints ValidationHigh Frequency DesignPower GatingPDN MethodologyPPA TargetsTiming Signoff

Early Applicant
Bengaluru, India

Skills:

DebuggingLogic DesignStaCircuit DesignPhysical VerificationPNRPhysical DesignEDA ToolsOptimizationRtl Design

Early Applicant
Bengaluru, India

Skills:

TclRoutingPerlNetlist2GDSII ImplementationPower Integrity AnalysisprimetimeFloor PlanningPhysical VerificationCadence ToolsCalibreCTSInnovusStaICC2Physical Design MethodologiesTkPlacementPT-PXsub-micron technology

Early Applicant
Bengaluru, India

Skills:

TclPythonPERLSeahawkSynthesisECO Timing ClosureLayout ClosureBlock-level and Full-chip Floor-planningprimetimePhysical VerificationIrCTSInnovusStaICC2Physical DesignTempusRTL2GDSII flowPlace And RouteTiming ConvergenceHigh Frequency Design Methodologies

Early Applicant
Bengaluru, India

Skills:

RoutingPhysical Design MethodologiesTcl tool scriptingRTL-to-GDSII implementationDDR design knowledgeprimetimePlacementCalibreGenusInnovusfloorplanningMultiTap-CTS

Early Applicant
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