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Showing 6 jobs
Skills:
test environments , Test Cases, Regression systems, Low-power design verification, Industry-standard simulators, Verification methodology, Revision control systems, Verification testbenches, Functional coverage, systemverilog
Skills:
Bash, Pcie, Perl, Python, Tcl, CHI, Ace, Uvm, systemverilog, Axi
Skills:
System Verilog, SV UVM based test benches, scripting languages such as Perl, HDLs like Verilog, debugging RTL TB issues using Verdi or similar tools
Skills:
Scala, Python, System Verilog, Chisel, Uvm
Skills:
Verilog, Python, Tcl, UVM verification methodology, Synopsys VCS, VHDL, Cadence Xcelium, Questa, systemverilog
Skills:
Makefile, Windows, Linux, Perl, Python, IP-level ASIC verification, simulation profiling, UVM methodology, UVM testbenches, systemverilog, formal verification, Efficiency Improvement, UVM-based verification frameworks
