routing, Signal Integrity, CTS, floorplanning, Timing Closure, IR EM and variability analysis, Placement, low-power design, ASIC SOC physical design implementation, Physical Verification

hardware engineering , Perl Scripting, Sta, Circuit Level Comprehension, Low Power Flow, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, IC design, Verification, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Constraints Validation, High Frequency Design, Power Gating, PDN Methodology, PPA Targets, Timing Signoff

Static Timing Analysis, Routing, Scripting, Extraction, EM, Ir, Floor-plan Physical Implementation, Physical Design, primetime, Placement, Design Compiler, DRC, Power-plan Synthesis, LVS, Cadence Genus, Formal Equivalence, Physical Verification, CTS, Innovus, PNR tools, ICC2, Mentor Graphics Calibre, Synopsys Fusion Compiler, Crosstalk Analysis, Apache Redhawk, Timing Closure, RTL to GDS2 flow, StarRC

redhawk , primetime, PDN methodology, floorplanning, physical design implementation, STA constraints, Tempus, Cadence Innovus, IR EM mitigation, Physical Verification, Voltus, signoff tools, Synopsys ICC2

Static Timing Analysis, Routing, Scripting, Cadence Genus, EM, Ir, Floor-plan Physical Implementation, primetime, Physical Design, Placement, DRC, Design Compiler, Extraction, Power-plan Synthesis, LVS, Formal Equivalence, Physical Verification, Innovus, PNR tools, ICC2, Mentor Graphics Calibre, Crosstalk Analysis, Synopsys Fusion Compiler, Apache Redhawk, Timing Closure, RTL to GDS2 flow, StarRC

synopsys tools , Tcl Scripting, Asic Physical Design, place-and-route, IC Compiler, Timing Closure, Design Compiler, Fusion Compiler, sign-off, Power Planning, floorplanning

layout verification , Tcl, static timing analysis, Python, Perl, Floor Planning, physical design tools, noise analysis, RTL to GDS workflows, equivalence verification, Clock Tree Synthesis

redhawk , Scripting Languages, Python, Perl, Tcl, power analysis, primetime, PrimeClouser, Tempus, Cadence Innovus, manufacturing sign-off, DFT insertion, Voltus, ASIC SoC physical design, Calibre, EDA Tools, low-power design, EM IR analysis, advanced nodes, multi-clock domain handling, Timing Analysis, Physical Verification, reliability checks, Signal Integrity