Unix, Shell, C, Linux, Perl, Verilog, Python, Uvm, systemverilog

EDA design tools, mixed-signal design, Power Management ICs, silicon evaluation and validation, Virtuoso Custom IC Environment, PDKs, LDMOS BCD process technologies, Cadence Tools

static timing analysis, LINT, Logic Synthesis, Dft, cdc, formal verification, Cadence-based ASIC design environments, low-power design methodologies, micro-architecture development, SystemVerilog RTL design

C, Uart, Spi, Shell, Verilog, Ethernet, I2c, Python, Systemc, Tcl, SVI3, systemverilog, Axi, formal verification, DMA, UVM-based testbench development, AHB, power-aware verification UPF, NoC bus and interconnect verification

Linux O.S., System Verilog, Python, Perl, Networking Protocols, Arm Assembly, Object-Oriented Design, Uvm, EDA Verification tools

static timing analysis, Dft, low-power design methodologies, LINT, Cadence-based ASIC design environments, micro-architecture development, SystemVerilog RTL design, formal verification, Logic Synthesis, cdc

C, Vcs, FPGA Design, Perl, Unix Shell Script, System Verilog, Python, Tcl, LINT, Synopsys simulators, Synthesis, RTL validation

C++, Soc, Python, Rtl Design, systemverilog, Uvm, formal verification, Simulation, CPU architecture, AMBA protocols