Principal Design Engineer

Key Responsibilities

Methodology Strategy

• Define and own the long-term DV architecture for processor verification.
• Ensure scalability across multiple processor variants and generations.

Verification Infrastructure

• Architect simulation testbenches in C/C++/RTL.
• Lead the development of reusable UVM-based verification environments.

Advanced Verification

• Champion integration of formal verification techniques.
• Implement AI-driven coverage analysis and advanced verification metrics.

Cross-Functional Collaboration

• Partner with microarchitecture, RTL design, and software teams.
• Align verification plans with ISA and SoC requirements.

Mentorship & Leadership

• Provide technical direction and set standards for quality and metric-driven verification (MDV).
• Guide and mentor global verification teams.