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Skills:
rtl verification , Verilog, reset strategy, SoC design flow, Simulation, timing considerations, datapath design, systemverilog, FSM design, Rtl Design, Axi, APB, debugging methodologies, BUS Protocols, AHB, clock-domain handling
Skills:
rtl verification , Verilog, AHB, SoC design flow, debugging methodologies, systemverilog, datapath design, reset strategy, Rtl Design, clock-domain handling, timing considerations, FSM design, APB, Axi, BUS Protocols, Simulation
