Usb, Mac, Perl, Pcie, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

Fpga, Logic Design, Verilog, Sta, Synthesis, Power product design, TCL scripts, Scan Insertion, Timing Analysis, design constraints, Uvm, ATPG generation, regression frameworks, formal verification, Timing Constraints, synthesis scripts, ABV, RTL Coding, micro-architecture, Functional Verification, System-Verilog, Digital Verification

Shell, Version Control Systems, Scripting, System Verilog, Python, Soc Architecture, Perl, performance features, functional and code coverage methodologies, Advanced SystemVerilog, X86 based SOC DV, Uvm, coverage closure, Security, BFMs, UVCs, power management, regression automation, memory subsystems, Debug, interconnects, SoC IP verification environments, Asic Design Verification, debugging skills, SoC verification methodologies, simulation and verification tools, VIPs

Tcl, Shell scripting, Python, Perl, Debugging, Uvm, systemverilog, Mixed-Signal Verification

code coverage , Scoreboards, Functional coverage, Assertions, RTL verification using Verilog and SystemVerilog, Constrained-random verification environments, Verification closure methodologies, Testbenches, Regression management, Coverage-driven verification techniques, Developing verification plans, Digital Verification

Tcl Scripting, Doors, Knowledge of Hardware Board and different components like ADC DAC Serial Memory, DO-254 development process, Electronics Electrical Engineering, Hardware system design knowledge of digital logic, RTL development using VHDL, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, FPGA Synthesis Place and Route, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, Requirement analysis and validation, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA design tools like Libero