Perl, Shell scripting, Python, UVM Universal Verification Methodology, PCIe protocol, Debugging RTL and gate level simulation issues, systemverilog

IP SoC verification, ASIC-SoC design verification, systemverilog

Regression Analysis, Cadence Xcelium, Top-Level Verification, wreal Modeling, model validation, Cadence VIVA, Schematic-Level Correlation, Uvm, Coverage-Driven Verification, Analog Circuit Fundamentals, Waveform Debug, SV-RNM, Verification Planning, Cadence ADE Assembler, Simulation Debug, SoC AMS Verification, Digital Design Flow, Mixed-Signal SoC Integration, systemverilog, Verilog-AMS, Cadence SimVision, Cadence Virtuoso, AMS Verification Methodology, Mixed-Signal Verification

Asic, Vlsi Design, SoC Verification

Perl, Verilog, System Verilog, Python, Tcl, Mentor Questa, Cadence Xcelium, CHI, Ace, Synopsys VCS, Axi, AMBA, VHDL, RISC-V instruction set architecture, APB, UVM-based testbenches

Dsp, System Verilog, Assembly level testcases, formal verification, Assertions, Digital Design, Uvm, Asic Design Verification, Processor Architecture, NPU, Debug, Gate-Level Simulation, Power aware verification

Perl, Verilog, Python, System Verilog, Tcl, Dft, DV, Uvm

Perl, Pcie, Ethernet, Shell scripting, Python, CHI, Ace, USB 3.x, RISC-V, Uvm, Assertions, systemverilog, Axi, USB4, CXL, DDR5, DDR4, SVA

Pcie, Perl, Python, AMBA, Axi, APB, AHB, System Verilog assertions, systemverilog