redhawk , Perl, Tcl, Dc, Deep sub-micron designs, Pt, Logic equivalence checking, Formality, VSLP, LVS, ICC, STA timing, Physical Design, Calibre, Timing Closure, Synthesis, SOC design, DRC, Place And Route, Low Power checking

layout verification , Computer Engineering, System Verilog, Tcl, low-power designs, Electrical Engineering, Computer Science, design rules, Vlsi Design

power integrity , Routing, floorplanning, Crosstalk Analysis, Timing Optimization, Cadence Innovus, LVS, ECO Engineering Change Order, Signal Integrity Closure, Physical Verification, Physical Design, DRC, EMIR Analysis