bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, Specman E, hierarchical memory subsystems, Debug, IP subsystem SoCs, congestion control, regression systems, systemverilog, vector processing units, full verification life cycle, revision control systems, AI ML Accelerators, constrained-random verification environments, packet processing, Verification

AMBA protocol knowledge, Good debugging skills, SV, Low speed interface protocols, SoC Verification, UMV

C, Ovm, virtualization, Perl, Python, Tcl, Client Server centric CPU features, SystemVerilog Assertions, Validation using Emulation and FPGA HW platforms, cache controllers, x86 assembly, semi randomized test generators, Uvm, systemverilog, validation strategy development, memory coherency, debugging test failures, power management, AI based methodologies in Validation, coverage driven Validation methodologies

Perl, Verilog, Python, Tcl, Synopsys VCS, Mentor Questa, Cadence Xcelium, VHDL, Uvm, SVA, systemverilog